1. Field of the Invention
The present invention relates to computer architectures. More specifically, the present invention relates to reconfigurable computer architectures.
2. Description of the Related Art
Most processing operations are currently performed using a fixed hardware architecture on which programmable software is executed. However, many processes are more readily implemented in hardware. For these operations, dedicated hardware can typically execute a given algorithm 2-3 orders of magnitude faster and more efficiently than software. Unfortunately, dedicated hardware is inflexible and can not easily be changed to perform functions other than those for which it was originally designed. Accordingly, reconfigurable computers have been developed as a compromise between the processing speed afforded by dedicated hardware and the flexibility afforded by software.
Reconfigurable computers consist of a multiplicity of programmably interconnected elements, whose functions are also programmable. Reconfigurable computers can be either fine-grained or coarse-grained. Fine-grained architectures, e.g., Field Programmable Gate Arrays (FPGAs), consist of thousands or millions of very simple Boolean functions connected by an elaborate programmable interconnection scheme. Coarse-grained architectures consist of tens to hundreds of complex elements, such as 8, 16, or 32 bit arithmetic operators, controllers, or even general-purpose processors.
In accordance with conventional teachings, interconnection among elements is commonly implemented as an X-Y mesh of data links, either 1) busses, to which elements can optionally connect, or 2) point-to-point links. Unfortunately, there are costs associated with the additional components required to provide for reconfigurability of reconfigurable computers constructed in accordance with conventional teachings. That is, reconfigurable computers constructed in accordance with conventional teachings tend to consume too much space, i.e., die area, on an integrated circuit; tend to be too slow and tend to consume too much power for many current applications.
Accordingly, a need remains in the art for more efficient ways to implement reconfigurable computers while at the same time retaining good flexibility of configuration. Specifically, a need remains in the art for a reconfigurable computer architecture that is fast while consuming less die area and power relative to reconfigurable computers implemented in accordance with conventional teachings.